Regular Logic Fabrics for Via Patterned Gate Arrays

As transistor feature sizes scale below 100nm, the costs of standard-cell-based application specific integrated circuits (ASICs) are increasing so rapidly that fewer products have sufficient volume to justify the high non-recurring engineering (NRE) costs. Consequently, more designs are relying on fully programmable devices such as field programmable gate arrays (FPGAs). Unfortunately, such fully programmable devices generally have much inferior power-delay performance when compared with standard-cell-based ASICs. In this report, we propose a new form of regular logic fabric that is customizable by just a few via masks to provide implementation simplicity and NRE costs comparable to an FPGA, but with power-delay performance closer to a standard-cell-based ASIC. We discuss the design and analysis of a few lookup tables (LUTs) similar to those used in FPGAs, but restructured for via-patternability and better power-delay performance. We also show that one of these via-patterned LUTs could be used very efficiently in dual-Vdd designs for VPGAs. We demonstrate that the most efficient configurable logic blocks (CLBs) for VPGAs would heterogeneous, containing LUTs and simple logic gates. Finally, we present a few implementation examples of VPGAs.